
module nios2soc (
	clk_clk,
	cy7c68013a_if_module_0_conduit_end_cha_fifo_data,
	cy7c68013a_if_module_0_conduit_end_cha_fifo_rdempty,
	cy7c68013a_if_module_0_conduit_end_cha_fifo_rdreq,
	cy7c68013a_if_module_0_conduit_end_chb_fifo_data,
	cy7c68013a_if_module_0_conduit_end_chb_fifo_rdempty,
	cy7c68013a_if_module_0_conduit_end_chb_fifo_rdreq,
	cy7c68013a_if_module_0_conduit_end_la_fifo_data,
	cy7c68013a_if_module_0_conduit_end_la_fifo_rdempty,
	cy7c68013a_if_module_0_conduit_end_la_fifo_rdreq,
	cy7c68013a_if_module_0_conduit_end_flaga_raw,
	cy7c68013a_if_module_0_conduit_end_flagc_raw,
	cy7c68013a_if_module_0_conduit_end_flagb_raw,
	cy7c68013a_if_module_0_conduit_end_slwr,
	cy7c68013a_if_module_0_conduit_end_slrd,
	cy7c68013a_if_module_0_conduit_end_sloe,
	cy7c68013a_if_module_0_conduit_end_pktend,
	cy7c68013a_if_module_0_conduit_end_fifoadr,
	cy7c68013a_if_module_0_conduit_end_fd,
	cy7c68013a_if_module_0_conduit_end_soc_ready,
	pio_0_external_connection_export,
	reset_reset_n,
	scope_module_0_conduit_end_chb_fifo_data,
	scope_module_0_conduit_end_chb_fifo_rdempty,
	scope_module_0_conduit_end_chb_fifo_rdreq,
	scope_module_0_conduit_end_cha_fifo_data,
	scope_module_0_conduit_end_cha_fifo_rdempty,
	scope_module_0_conduit_end_cha_fifo_rdreq,
	scope_module_0_conduit_end_adc_clk,
	scope_module_0_conduit_end_chb_data,
	scope_module_0_conduit_end_cha_data,
	spi_0_external_MISO,
	spi_0_external_MOSI,
	spi_0_external_SCLK,
	spi_0_external_SS_n);	

	input		clk_clk;
	input	[15:0]	cy7c68013a_if_module_0_conduit_end_cha_fifo_data;
	input		cy7c68013a_if_module_0_conduit_end_cha_fifo_rdempty;
	output		cy7c68013a_if_module_0_conduit_end_cha_fifo_rdreq;
	input	[15:0]	cy7c68013a_if_module_0_conduit_end_chb_fifo_data;
	input		cy7c68013a_if_module_0_conduit_end_chb_fifo_rdempty;
	output		cy7c68013a_if_module_0_conduit_end_chb_fifo_rdreq;
	input	[15:0]	cy7c68013a_if_module_0_conduit_end_la_fifo_data;
	input		cy7c68013a_if_module_0_conduit_end_la_fifo_rdempty;
	output		cy7c68013a_if_module_0_conduit_end_la_fifo_rdreq;
	input		cy7c68013a_if_module_0_conduit_end_flaga_raw;
	input		cy7c68013a_if_module_0_conduit_end_flagc_raw;
	input		cy7c68013a_if_module_0_conduit_end_flagb_raw;
	output		cy7c68013a_if_module_0_conduit_end_slwr;
	output		cy7c68013a_if_module_0_conduit_end_slrd;
	output		cy7c68013a_if_module_0_conduit_end_sloe;
	output		cy7c68013a_if_module_0_conduit_end_pktend;
	output	[1:0]	cy7c68013a_if_module_0_conduit_end_fifoadr;
	inout	[15:0]	cy7c68013a_if_module_0_conduit_end_fd;
	output		cy7c68013a_if_module_0_conduit_end_soc_ready;
	inout	[31:0]	pio_0_external_connection_export;
	input		reset_reset_n;
	output	[15:0]	scope_module_0_conduit_end_chb_fifo_data;
	output		scope_module_0_conduit_end_chb_fifo_rdempty;
	input		scope_module_0_conduit_end_chb_fifo_rdreq;
	output	[15:0]	scope_module_0_conduit_end_cha_fifo_data;
	output		scope_module_0_conduit_end_cha_fifo_rdempty;
	input		scope_module_0_conduit_end_cha_fifo_rdreq;
	output		scope_module_0_conduit_end_adc_clk;
	input	[7:0]	scope_module_0_conduit_end_chb_data;
	input	[7:0]	scope_module_0_conduit_end_cha_data;
	input		spi_0_external_MISO;
	output		spi_0_external_MOSI;
	output		spi_0_external_SCLK;
	output	[2:0]	spi_0_external_SS_n;
endmodule
